Refresh Pending Link Special Proc Clock Out Link123 Special Link In0 Link Out1 Link In2 Event Ack GND Mem Wait Proc Speed Select0 Clock In Event Waiting Link0 Special Link Out0 Link Out2 Link Out3 Event Req Mem Req not Mem WrB3 GND VDD Cap Minus Cap Plus VDD Link In1 Link In3 Mem Config Mem Granted not Mem WrB1 Error Proc Speed Select2 Error In not Mem Rf not Mem WrB2 not Mem WrB0 Disable Int RAM Boot From ROM Reset not Mem Rd not Mem S0 VDD Proc Speed Select1 Analyse Mem AD31 not Mem S3 not Mem S2 not Mem S4 Mem AD30 GND Mem AD27 Mem not WrD0 GND not Mem S1 Mem AD29 Mem AD25 Mem AD23 VDD Mem AD16 Mem AD12 Mem AD8 Mem AD4 Mem AD3 Mem not RfD1 Mem AD28 Mem AD24 Mem AD22 Mem AD19 Mem AD17 Mem AD13 GND Mem AD6 Mem AD5 Mem AD2 Mem AD26 Mem AD21 Mem AD20 Mem AD18 Mem AD15 Mem AD14 Mem AD11 Mem AD10 Mem AD9 Mem AD7 A21 A23 A25 A26 A30 A31 D2 D5 D6 D13 A5 A9 A11 A24 A29 GND D3 D7 VDD D14 A4 A6 A8 A22 A10 D0 D4 D9 D12 D16 GND A2 A3 A7 A27 D1 D8 D10 D15 D17 A17 A19 A18 A20 A28 D11 D18 D19 D20 D21 A16 A15 A14 A13 Reset Error D24 GND D23 D22 A12 not Mem WrB2 not Mem WrB0 GND Link In1 Link Speed D31 D27 D26 D25 not Mem WrB3 Mem Wait Mem Req Link Out3 Link In0 Proc Clock Out GND Proc Speed Select1 D30 D28 not Mem WrB1 Mem Granted Event Req Link In2 Link Out1 Event Waiting Clock In Boot From ROM Analyse D29 not Mem CE Event Ack Link In3 Link Out2 Link Out0 VDD Cap Plus Cap Minus Proc Speed Select0 Proc Speed Select2 DoNot Wire Link Special Proc Clock Out Link123 Special Link In0 Link Out1 Link In2 Event Ack GND Mem Wait Proc Speed Select0 Clock In DoNot Wire Link0 Special Link Out0 Link Out2 Link Out3 Event Req Mem Req not Mem WrB3 GND VDD Cap Minus Cap Plus VDD Link In1 Link In3 Mem Config Mem Granted not Mem WrB1 Error Proc Speed Select2 Error In not Mem Rf not Mem WrB2 not Mem WrB0 Disable Int RAM Boot From ROM Reset not Mem Rd not Mem S0 VDD Proc Speed Select1 Analyse Mem AD31 not Mem S3 not Mem S2 not Mem S4 Mem AD30 GND Mem AD27 Mem not WrD0 GND not Mem S1 Mem AD29 Mem AD25 Mem AD23 VDD Mem AD16 Mem AD12 Mem AD8 Mem AD4 Mem AD3 Mem not RfD1 Mem AD28 Mem AD24 Mem AD22 Mem AD19 Mem AD17 Mem AD13 GND Mem AD6 Mem AD5 Mem AD2 Mem AD26 Mem AD21 Mem AD20 Mem AD18 Mem AD15 Mem AD14 Mem AD11 Mem AD10 Mem AD9 Mem AD7 Refresh Pending Link Special Proc Clock Out Link123 Special Link In0 Link Out1 Link In2 Event Ack GND Mem Wait Proc Speed Select0 Clock In Event Waiting Link0 Special Link Out0 Link Out2 Link Out3 Event Req Mem Req not Mem WrB3 GND VDD Cap Minus Cap Plus VDD Link In1 Link In3 Mem Config Mem Granted not Mem WrB1 Error Proc Speed Select2 Error In not Mem Rf not Mem WrB2 not Mem WrB0 Disable Int RAM Boot From ROM Reset not Mem Rd not Mem S0 VDD Proc Speed Select1 Analyse Mem AD31 not Mem S3 not Mem S2 not Mem S4 Mem AD30 GND Mem AD27 Mem not WrD0 GND not Mem S1 Mem AD29 Mem AD25 Mem AD23 VDD Mem AD16 Mem AD12 Mem AD8 Mem AD4 Mem AD3 Mem not RfD1 Mem AD28 Mem AD24 Mem AD22 Mem AD19 Mem AD17 Mem AD13 GND Mem AD6 Mem AD5 Mem AD2 Mem AD26 Mem AD21 Mem AD20 Mem AD18 Mem AD15 Mem AD14 Mem AD11 Mem AD10 Mem AD9 Mem AD7 DoNot Wire Link Special Proc Clock Out Link123 Special Link In0 Link Out1 Link In2 Event Ack GND Mem Wait Hold To GND Clock In DoNot Wire Link0 Special Link Out0 Link Out2 Link Out3 Event Req Mem Req not Mem WrB3 GND VDD Cap Minus Cap Plus VDD Link In1 Link In3 Mem Config Mem Granted not Mem WrB1 Error Hold To GND Hold To GND not Mem Rf not Mem WrB2 not Mem WrB0 Disable Int RAM Boot From ROM Reset not Mem Rd not Mem S0 VDD Hold To GND Analyse Mem AD31 not Mem S3 not Mem S2 not Mem S4 Mem AD30 GND Mem AD27 Mem not WrD0 GND not Mem S1 Mem AD29 Mem AD25 Mem AD23 VDD Mem AD16 Mem AD12 Mem AD8 Mem AD4 Mem AD3 Mem not RfD1 Mem AD28 Mem AD24 Mem AD22 Mem AD19 Mem AD17 Mem AD13 GND Mem AD6 Mem AD5 Mem AD2 Mem AD26 Mem AD21 Mem AD20 Mem AD18 Mem AD15 Mem AD14 Mem AD11 Mem AD10 Mem AD9 Mem AD7 Refresh Pending Link Special Proc Clock Out Link1 Special Link In0 Link Out1 Hold To GND Event Ack GND Mem Wait Proc Speed Select0 Clock In Event Waiting Link0 Special Link Out0 DoNot Wire DoNot Wire Event Req Mem Req not Mem WrB3 GND VDD Cap Minus Cap Plus VDD Link In1 Hold To GND Mem Config Mem Granted not Mem WrB1 Error Proc Speed Select2 Error In not Mem Rf not Mem WrB2 not Mem WrB0 Disable Int RAM Boot From ROM Reset not Mem Rd not Mem S0 VDD Proc Speed Select1 Analyse Mem AD31 not Mem S3 not Mem S2 not Mem S4 Mem AD30 GND Mem AD27 Mem not WrD0 GND not Mem S1 Mem AD29 Mem AD25 Mem AD23 VDD Mem AD16 Mem AD12 Mem AD8 Mem AD4 Mem AD3 Mem not RfD1 Mem AD28 Mem AD24 Mem AD22 Mem AD19 Mem AD17 Mem AD13 GND Mem AD6 Mem AD5 Mem AD2 Mem AD26 Mem AD21 Mem AD20 Mem AD18 Mem AD15 Mem AD14 Mem AD11 Mem AD10 Mem AD9 Mem AD7 Cap Plus Link0 Special Proc Clock Out VDD Link In0 Link Out1 Link Out2 Link In2 Link In3 Disable Int RAM Proc Speed Select2 Clock In Link Special Link123 Special Link Out0 Link In1 Link Out3 Event Req Proc Speed Select0 Analyse Reset Boot From ROM Cap Minus Event Ack Mem Wait Mem Req Error Proc Speed Select1 Mem BAcc Mem Granted Mem D0 Mem D1 GND not Mem CE Mem D2 Mem D3 not Mem WrB1 not Mem WrB0 Mem D4 GND Mem A2 Mem A0 Mem D5 Mem D7 Mem D9 Mem A5 Mem A6 Mem A1 Mem D6 Mem D10 Mem D12 Mem D14 Mem A15 Mem A13 Mem A10 Mem A8 Mem A7 Mem A3 Mem D8 Mem D11 Mem D13 Mem D15 Mem A14 VDD Mem A12 Mem A11 Mem A9 Mem A4 Cap Plus Link0 Special Proc Clock Out VDD Link In0 Link Out1 Link Out2 Link In2 Link In3 Disable Int RAM Hold To GND Clock In Link Special Link123 Special Link Out0 Link In1 Link Out3 Event Req Hold To GND Analyse Reset Boot From ROM Cap Minus Event Ack Mem Wait Mem Req Error Hold To GND Mem BAcc Mem Granted Mem D0 Mem D1 GND not Mem CE Mem D2 Mem D3 not Mem WrB1 not Mem WrB0 Mem D4 GND Mem A2 Mem A0 Mem D5 Mem D7 Mem D9 Mem A5 Mem A6 Mem A1 Mem D6 Mem D10 Mem D12 Mem D14 Mem A15 Mem A13 Mem A10 Mem A8 Mem A7 Mem A3 Mem D8 Mem D11 Mem D13 Mem D15 Mem A14 VDD Mem A12 Mem A11 Mem A9 Mem A4 Cap Plus Link0 Special Proc Clock Out VDD Link In0 Link Out1 Link Out2 Link In2 Link In3 Hold To GND Hold To GND Clock In Link Special Link123 Special Link Out0 Link In1 Link Out3 Event Req Hold To GND Analyse Reset Boot From ROM Cap Minus Event Ack Mem Wait Mem Req Error Hold To GND Mem BAcc Mem Granted Mem D0 Mem D1 GND not Mem CE Mem D2 Mem D3 not Mem WrB1 not Mem WrB0 Mem D4 GND Mem A2 Mem A0 Mem D5 Mem D7 Mem D9 Mem A5 Mem A6 Mem A1 Mem D6 Mem D10 Mem D12 Mem D14 Mem A15 Mem A13 Mem A10 Mem A8 Mem A7 Mem A3 Mem D8 Mem D11 Mem D13 Mem D15 Mem A14 VDD Mem A12 Mem A11 Mem A9 Mem A4 Boot From ROM Cap Plus Clock In Hold To GND Link Out0 Link In0 Link In1 Link Speed Event Ack PB7 VDD Analyse Cap Minus Error Proc Clock Out Link Out1 Event Req Hold To GND PB5 PB4 AD6 AD7 Reset PB6 PB2 PB1 AD5 AD4 PB3 PB0 AD3 AD2 VDD PA7 AD1 AD0 PA5 PA6 notCE RnotW PA2 PA4 ALE GND A6 Vin GND PA3 Wait A5 A3 A1 Disable Int ROM Late Read Data Phase Up Phase Down PA1 A7 A4 A2 A0 Write Clock not Write Gate Early not Write Data not Index PA0 Link In2 Link In4 GND Link In6 Cap Plus Clock In Link In14 Link In11 Link In10 Link Out10 Link Out5 Link In0 Link In1 Link In5 Cap Minus Link In15 Link In13 Link In9 Link Out8 VDD Link Out4 Link Out6 Link Out7 Link In3 Link In7 VDD Link In12 Link In8 Link Out9 Link Out12 Link Out3 GND VDD Link Out11 GND Link Out13 Link Out0 Link Out2 Link Out1 Link Out14 Link Out15 Link Out16 Link Out31 Link Out30 Link Out29 Link Out18 Link Out19 Link Out17 Link Out28 VDD Link Out26 GND VDD Link Out20 Link Out27 Link Out24 Config LinkIn Link In28 Link In24 Link In22 Link In17 DoNot Wire Link Out23 Link Out21 GND Config LinkOut Link In31 Link In27 Link In25 Link In23 Link In19 Reset Link Speed Link Out22 Link Out25 Link In30 Link In29 Link In26 GND VDD Link In21 Link In20 Link In18 Link In16 AD Bus16 AD Bus18 AD Bus20 AD Bus21 Reset VSync VDD Pix DataB7 Pix DataA7 Pix DataD5 AD Bus11 AD Bus14 AD Bus15 AD Bus19 AD Bus23 GND Pix DataD7 Pix DataD6 Pix DataB6 Pix DataB5 AD Bus10 AD Bus12 AD Bus13 AD Bus17 AD Bus22 CorH Sync Pix DataC7 Pix DataC6 Pix DataA6 Pix DataD4 AD Bus7 AD Bus8 AD Bus9 Pix DataC5 Pix DataA5 Pix DataC4 AD Bus4 AD Bus6 AD Bus5 Pix DataB4 Pix DataA4 Pix DataD3 AD Bus3 VDD GND Pix DataB3 Pix DataA3 Pix DataC3 AD Bus2 AD Bus0 not Serial Clk Pix DataD2 VDD GND AD Bus1 Frame Inactive notCS Bus Granted Blue Pix DataA0 Pix DataB1 CBlank Pix DataA2 Pix DataC2 not ShiftClk RnotW Cap Minus Bus Req GND Iref Pix DataD0 Pix DataD1 AVDD Pix DataB2 Transfer Cap Plus Clock In VDD Green Red Pix DataB0 Pix DataC0 Pix DataA1 Pix DataC1