Performance improvement with the INMOS Dx305 Occam 2 toolset

March 1993
INMOS document number: 72-TDS-379-00
54 Pages

About this document

This document provides advice about how to maximize the performance of the toolset. It brings together information provided in other toolset documents particularly from the Language and Libraries Reference Manual.

The document describes the layout of code and data in memory for programs developed with the DX305 occam 2 Toolset. It then goes on to describe methods of improving code in order to:

Note: details of how to manipulate the software virtual through-routing mechanism are given in the User Guide.

Contents

	Preface
		Host versions
		About this document
		About the toolset documentation set
		Other documents
		FORTRAN toolset
		Documentation conventions

1	Introduction
	1.1	Transputer architecture

2	Trade-offs and Issues
	2.1	Space versus time
	2.2	On-chip RAM
	2.3	Basic code generation techniques
	2.4	Processor classes and types
	2.5	Interactive debugging
	2.6	Virtual routing
	2.7	Error modes
	2.8	Vector space
	2.9	Alias checking
	2.10	Usage checking
	2.11	Memory layout
	2.12	When there isn't enough on-chip RAM

3	Obtaining information

4	Command line switches
	4.1	Compiler command line switches
	4.2	Linker command line switches
	4.3	Linker directives
	4.4	Configurer command line switches
	4.5	Configuration language attributes for optimizing memory
		4.5.1	Ordering attributes
		4.5.2	Location attributes
		4.5.3	Reserved attribute
	4.6	Collector command line switches

5	Compiler optimizations

6	Source code optimizations
	6.1	Compiler workspace layout
	6.2	Compiler code layout
	6.3	Abbreviations
		6.3.1	Abbreviations - They should not be too trivial
		6.3.2	Abbreviations - Removing range-checking code
		6.3.3	Abbreviations - Loop unrolling
	6.4	Vectorspace
	6.5	Beware the PLACE statement
	6.6	Abbreviating PLACED objects
	6.7	Block move
	6.8	Use TIMES
	6.9	Retyping - accelerating byte manipulation
	6.10	Scoping of variables
	6.11	Use the whole language
	6.12	INLINE procedures and functions
	6.13	Access to non-local variables
	6.14	Access to formal parameters
	6.15	Pre-evaluate expressions
	6.16	Conditional expressions
	6.17	Array subscripts
	6.18	INT16s
	6.19	ALTs
	6.20	Use of ASSERT()
	6.21	Transputer scheduler

7	Summary
	7.1	Optimizing for code size
	7.2	Removing run-time checks
	7.3	Placing arrays in on-chip RAM
	7.4	Placing code in on-chip RAM
	7.5	Building benchmarks

8	Maximizing multiprocessor performance
	8.1	Maximizing link performance
		8.1.1	Decoupling communication and computation
		8.1.2	Prioritization
	8.2	Large link transfers

9	Dynamic load balancing and processor farms

	Index

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