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Transputer Development and iq Systems Databook

Second Edition 1991
INMOS document number: 72-TRN-219-01
500 Pages

© INMOS Limited 1991. INMOS reserves the right to make changes in specifications at any time and without notice. The information furnished by INMOS in this publication is believed to be accurate; however, no responsibility is assumed for its use, nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted under any patents, trademarks or other rights of INMOS.

Preface

frontcover 72-TRN-219-01

Development tools and system products are important and developing areas of application for INMOS devices. The Transputer Development and iq Systems Databook has been published to provide detailed information on the INMOS product range.

The databook comprises an overview, engineering data and applications information for the current range of development tools and systems products.

INMOS provide a wide range of development tools including compilers, toolsets and development kits. A diverse range of software is also available. INMOS systems products provide powerful development platforms for system designers interested in high density, high performance, design simplicity and cost effectiveness.

In addition to development tools and systems products, the INMOS product range also includes transputer products and high performance graphics devices. For further information concerning INMOS products please contact your local SGS-THOMSON sales outlet.

Contents

Preface

1 System Products overview
	1.1	Introduction
	1.2	Innovation and Quality
	1.3	TRAMS (TRAnsputer Modules)
		1.3.1	Standard Interface
		1.3.2	Upgradability
		1.3.3	Flexibility
		1.3.4	Evaluation
	1.4	Quality and Reliability

Development Systems

Software Development Tools


2 occam 2 Toolset
	2.1	Introduction
	2.2	Mapping occam Programs Onto Transputer Networks
	2.3	Product Overview
		2.3.1	occam 2 development system
		2.3.2	Libraries
			occam compiler library
			snglmath.lib, dblmath.lib
			tbmaths.lib
			string.lib
			hostio.lib
			streamio.lib
			msdos.lib
			crc.lib
			convert.lib
			xlink.lib
			debug.lib
		2.3.3	Mixed language programs
		2.3.4	Debugging
			Interactive symbolic debugging
			Post-mortem symbolic debugging
			T425 simulation
		2.3.5	Optimised code generation
		2.3.6	Assembler inserts
		2.3.7	D700 transputer development system support
		2.3.8	Improvements over previous releases
	2.4	occam Toolset Product Components
		2.4.1	Documentation
		2.4.2	Software Tools
		2.4.3	Software libraries
		2.4.4	Source code
	2.5	Product Variants
		2.5.1	IMS D7205 IBM PC and NEC PC version
			Operating requirements
			Distribution media
		2.5.2	IMS D6205 VAX VMS version
			Operating requirements
			Distribution media
		2.5.3	IMS D5205 Sun 3 version, IMS D4205 Sun 4 version
			Operating requirements
			Distribution media
	2.6	Licensing Information
	2.7	Problem Reporting And Field Support

3 ANSI C Toolset
	3.1	Introduction
	3.2	Product Overview
		3.2.1	How programs are built
		3.2.2	ANSI C compilation system
			Compiler operation
			ANSI conformance
			Optimised code generation
			Libraries
			Mixed language programs
			Assembler inserts
		3.2.3	Target systems
		3.2.4	Support for parallelism
		3.2.5	Debugging
			T425 simulation
			Interactive symbolic debugging
			Post-mortem symbolic debugging
		3.2.6	Improvements over previous releases
	3.3	ANSI C Toolset Product Components
		3.3.1	Documentation
		3.3.2	Software Tools
		3.3.3	Software libraries
	3.4	Product Variants
		3.4.1	IMS D7214 IBM PC version
			Operating requirements
			Distribution media
		3.4.2	IMS D6214 VAX VMS version
			Operating requirements
			Distribution media
		3.4.3	IMS D5214 Sun 3 version, IMS D4214 Sun 4 version
			Operating requirements
			Distribution media
	3.5	Error Reporting And Field Support

4 Glockenspiel C++
	4.1	Product Overview
		4.1.1	C++
		4.1.2	Use with the INMOS ANSI C toolset
	4.2	Glockenspiel C++ Product Components
		4.2.1	Documentation
		4.2.2	Software tools
		4.2.3	Software Libraries
	4.3	Product Variants
		4.3.1	IMS D7217 IBM PC version
			Cross-development operating requirements
			Native development operating requirements
			Distribution media
		4.3.2	IMS D6214 VAX VMS version
			Cross-development operating requirements
			Native development operating requirements
			Distribution media
			Licensing variants
		4.3.3	IMS D5217 Sun 3 version
			Cross-development operating requirements
			Native development operating requirements
			Distribution media
			Licensing variants
		4.3.4	IMS D4217 Sun 4 version
			Cross-development operating requirements
			Native development operating requirements
			Licensing variants
			Distribution media
	4.4	Error Reporting And Field Support

5 ANSI FORTRAN 77 Toolset
	5.1	Introduction
	5.2	Product Overview
		5.2.1	How programs are built
		5.2.2	ANSI FORTRAN compilation system
			Compiler operation
			ANSI conformance
			Optimised code generation
			Run-Time System
			Mixed language programs
		5.2.3	Target systems
		5.2.4	Support for parallelism
		5.2.5	Debugging
			T425 simulation
			Interactive symbolic debugging
			Post-mortem symbolic debugging
		5.2.6	Improvements over previous releases
	5.3	ANSI FORTRAN Toolset Product Components
		5.3.1	Documentation
		5.3.2	Software Tools
	5.4	Product Variants
		5.4.1	IMS D7216 IBM PC version
			Operating requirements
			Distribution media
		5.4.2	IMS D6216 VAX VMS version
			Operating requirements
			Distribution media
		5.4.3	IMS D5216 Sun 3 version, IMS D4214 Sun 4 version
			Operating requirements
			Distribution media
	5.5	Error Reporting And Field Support

6 ALSYS Ada Compiler
	6.1	Product Overview
	6.2	Product Highlights
		6.2.1	Supports easy implementation of distributed Ada applications
		6.2.2	Efficient sharing of Ada Libraries
		6.2.3	Generates high performance, compact application code
			Ada Code Generation
			Floating point support
			Ada Run Time
			Supports low level programming features
		6.2.4	Increased development productivity
		6.2.5	Advanced debugging support
		6.2.6	Ada predefined Input and Output
		6.2.7	Transfers the loadable Ada program to the target
	6.3	The Alsys Ada Compilation System
	6.4	Ada Compiler Toolset Product Components
		6.4.1	Documentation
			User's Guide
			Project Development Guide
			Installation Guide
			Ada Reference Manual
			Appendix F
			Application Developer's Guide
		6.4.2	Software Components
	6.5	Product Variants
		6.5.1	IBM PC Alsys Ada Compiler
			Operating requirements
			Distribution media
		6.5.2	VAX VMS Alsys Ada Compiler
			Operating requirements
			Distribution media
	6.6	Customer Support And Upgrade Services
	6.7	Alsys And Ada
			Alsys Offices and Addresses

Transputer Development Kits


7 Transputer Development Kits
	7.1	Transputer Development Kits

Systems Software

Board Support Software


8 IMS F000B VecTRAM library
	8.1	Introduction
	8.2	Product Overview
	8.3	Using IMS F000B
		8.3.1	Incorporation into a C program
		8.3.2	Incorporation into an occam program
	8.4	Supplied Routines
		8.4.1	Vector Absolute Value - Real
		8.4.2	Vector Addition - Real
		8.4.3	Vector Compare - Real
		8.4.4	Disable Co-processor Error Flags
		8.4.5	Vector Division - Real
		8.4.6	Vector Dot Product - Complex
		8.4.7	Vector Dot Product - Real
		8.4.8	Enable Co-processor Error Interrupts
		8.4.9	Fast Fourier Transform - Complex
		8.4.10	Finite Impulse Response (FIR) Filter
		8.4.11	Vector Floating Point to Integer (16-bit) Conversion
		8.4.12	Infinite Impulse Response (IIR) Filter - Complex
		8.4.13	Infinite Impulse Response (IIR) Filter - Real
		8.4.14	Matrix Multiplication - Complex
		8.4.15	Matrix Multiplication - Real
		8.4.16	Inverse Fast Fourier Transform - Complex
		8.4.17	Vector Integer(16-bit) to 32-bit floating-point Conversion
		8.4.18	Vector Log to the base 10 - Real
		8.4.19	Vector Magnitude - Complex
		8.4.20	Vector Magnitude Square - Complex
		8.4.21	Find the Element with the Maximum Value and Its Position - Real
		8.4.22	Vector Mean - Real
		8.4.23	Find the Element with the Minimum Value and Its Position - Real
		8.4.24	Vector Move - Bytes
		8.4.25	Vector Move - Words (32-bit)
		8.4.26	Vector Multiply - Complex
		8.4.27	Vector Multiply - Real
		8.4.28	Vector Power - Real
		8.4.29	Modify Co-processor Rounding Mode
		8.4.30	Vector Scale - Real
		8.4.31	Vector Square Root - Real
		8.4.32	Vector Subtract - Real
	8.5	Environment
	8.6	IMS F000B Product Components
		8.6.1	Distribution media
		8.6.2	Documentation
	8.7	Error Reporting And Field Support
	8.8	References

9 IMS F001B GPIB libraries
	9.1	Introduction
	9.2	Product Overview
		9.2.1	IMS F001B command format
			Summary of the IMS F001B commands
		9.2.2	Using IMS F001B
	9.3	Operating environment
	9.4	IMS F001 B Product Components
		9.4.1	Distribution media
		9.4.2	Documentation
	9.5	Error Reporting And Field Support

10 IMS F002B SCSI libraries
	10.1	Introduction
		10.1.1	SCSI overview
	10.2	Product Overview
		10.2.1	IMS B422 Device Driver
		10.2.2	Initialisation Interface
		10.2.3	Initiator Mode Interface
			Common Command Set
		10.2.4	Target Mode Interface
		10.2.5	Diagnostic tests
		10.2.6	Initialisation Interfaces
	10.3	Incorporation into a user program
			Incorporation of initiator mode into a user program
	10.4	Simple Initiator mode example
			Configuration
	10.5	List of supplied procedures
	10.6	Performance
	10.7	Compatibility
	10.8	Operating environment
	10.9	IMS F002B Product Components
		10.9.1	Distribution media
		10.9.2	Documentation
	10.10	Error Reporting And Field Support
	10.11	References

11 IMS F003A 2D Graphics libraries
	11.1	Introduction
	11.2	Product Overview
		11.2.1	Summary of the IMS F003 commands
	11.3	Using IMS F003
	11.4	IMS F003 Product Components
		11.4.1	Distribution media
		11.4.2	Documentation
		11.4.3	Operating environment
	11.5	Error Reporting And Field Support

12 IMS F007A DSP libraries and development tools
	12.1	Introduction
	12.2	Product Overview
		12.2.1	Library usage
		12.2.2	intgen - VecTRAM Interface Generation Utility
			Running the intgen utility
		12.2.3	ivtlink - VecTRAM Linker
	12.3	Supplied Routines
	12.4	Environment
	12.5	IMS F007A Product Components
		12.5.1	Distribution media
		12.5.2	Documentation
	12.6	Error Reporting And Field support
	12.7	References
	12.8	Ordering Information

13 Device Drivers and Motherboard Support Software
	13.1	Product overview
		13.1.1	Device driver
		13.1.2	INMOS server
		13.1.3	Transputer mapping software
		13.1.4	Switch setting support
	13.2	Product components summary
		13.2.1	Documentation
			User manual
		13.2.2	Software
			Device driver
			INMOS iserver (with sources)
			Transputer mapping tool
			Motherboard switch-setting software
	13.3	Product variants
		13.3.1	General operating requirements
		13.3.2	Distribution media
			IMS S217
			IMS S308
			IMS S708
			IMS S514
	13.4	OEM support

14 Network Support Software
	14.1	Introduction
	14.2	Product Overview
		14.2.1	Connecting transputers to computer networks
		14.2.2	Capabilities
		14.2.3	System configuration
		14.2.4	Support for INMOS development tools
		14.2.5	Support for INMOS Ethernet connection system (IMS B300)
		14.2.6	Support for mixed networks of machines
	14.3	Product Component Summary
		14.3.1	Documentation
			User Manual
		14.3.2	Software
			Extended INMOS iserver
			Connection server
			INMOS Ethernet box configuration program
	14.4	Product Variants
		14.4.1	IMS S707 IBM PC
			Operating requirements
			Boards supported
			Distribution media
		14.4.2	IMS S607 VAX VMS
			Operating requirements
			Distribution media
		14.4.3	IMS S507 Sun 3 and Sun 4
			Operating requirements
			Boards supported
			Distribution media
	14.5	Error Reporting And Field Support

Real Time Kernels and Operating Systems


15 VRTX32/T Real-time Executive
	15.1	Overview
			Deterministic Performance
			Distributed Environment
			Support

16 C Executive
	16.1	C Executive For The Transputer
	16.2	Benefits Of C Executive
	16.3	CE-VIEW
	16.4	Documentation
	16.5	Availability
	16.6	Licensing
	16.7	How To Order

Hardware Products

TRAnsputer Modules (TRAMS)


17 IMS B401 32Kbyte TRAM
	17.1	IMS B401 TRAM engineering data
		17.1.1	Introduction
		17.1.2	Pin descriptions
		17.1.3	Standard TRAM signals
			notError (pin 11)
			LinkspeedA and LinkspeedB (pins 6 and 7)
			Link signals
		17.1.4	Memory configuration
			Location of external memory
		17.1.5	Mechanical details
		17.1.6	Installation
		17.1.7	Specification
		17.1.8	Ordering Information

18 IMS B416 64Kbyte TRAM
	18.1	IMS B416 TRAM engineering data
		18.1.1	Introduction
		18.1.2	Pin descriptions
		18.1.3	Standard TRAM signals
			notError (pin 11)
			LinkspeedA and LinkspeedB (pins 6 and 7)
			Link signals
		18.1.4	Memory configuration
		18.1.5	Mechanical details
		18.1.6	Installation
		18.1.7	Specification
		18.1.8	Ordering Information

19 IMS B410 160Kbyte TRAM
	19.1	IMS B410 TRAM engineering data
		19.1.1	Description
		19.1.2	Pin descriptions
		19.1.3	Standard TRAM signals
			notError (pin 11)
			LinkspeedA and LinkspeedB (pins 6 and 7)
			Link signals
		19.1.4	Memory configuration
		19.1.5	Mechanical details
		19.1.6	Installation
		19.1.7	Specification
		19.1.8	Ordering Information

20 IMS B411 1MbyteTRAM
	20.1	IMS B411 TRAM engineering data
		20.1.1	Description
		20.1.2	Pin descriptions
		20.1.3	Standard TRAM signals
			notError (pin 11)
			LinkSpeedA and LinkSpeedB (pins 6 and 7)
			Link signals
		20.1.4	Memory configuration
		20.1.5	Mechanical details
		20.1.6	Installation
		20.1.7	Specification
		20.1.8	Ordering Information

21 IMS B404 2Mbyte TRAM
	21.1	IMS B404 TRAM engineering data
		21.1.1	Introduction
		21.1.2	Pin descriptions
		21.1.3	Standard TRAM signals
			notError (pin 11)
			LinkSpeedA and LinkSpeedB (pins 6 and 7)
			Link signals
		21.1.4	Subsystem signals
		21.1.5	Memory configuration
			Location of external memory
			Subsystem register locations
		21.1.6	Mechanical details
		21.1.7	Installation
		21.1.8	Specification
		21.1.9	Ordering Information

22 IMS B428 2Mbyte TRAM
	22.1	IMS B428 TRAM engineering data
		22.1.1	Introduction
		22.1.2	Pin descriptions
		22.1.3	Standard TRAM signals
			notError (pin 11)
			LinkSpeedA and LinkSpeedB (pins 6 and 7)
			Link signals
		22.1.4	Subsystem signals
		22.1.5	Memory configuration
			Subsystem register locations
		22.1.6	Mechanical details
		22.1.7	Installation
		22.1.8	Specification
			Notes
	22.2	Ordering Information

23 IMS B417 4Mbyte TRAM
	23.1	IMS B417 TRAM engineering data
		23.1.1	Introduction
		23.1.2	Pin descriptions
		23.1.3	Standard TRAM signals
			notError (pin 11)
			LinkSpeedA and LinkSpeedB (pins 6 and 7)
			Link signals
		23.1.4	Subsystem signals
		23.1.5	Memory configuration
			Location of external memory
			Subsystem register locations
		23.1.6	Mechanical details
		23.1.7	Installation
		23.1.8	Specification
		23.1.9	Ordering Information

24 IMS B426 4Mbyte TRAM
	24.1	Description
	24.2	Pin descriptions
			Notes:
	24.3	Standard TRAM signals
		24.3.1	notError (pin 11)
		24.3.2	LinkSpeedA and LinkSpeedB (pins 6 and 7)
		24.3.3	Link signals
	24.4	Memory configuration
	24.5	Mechanical details
	24.6	Installation
	24.7	Specification
			Notes
	24.8	Ordering Information

25 IMS B427 8Mbyte TRAM
	25.1	Description
	25.1.1	Pin descriptions
			Notes:
	25.1.2	Standard TRAM signals
		25.2	notError (pin 11)
		25.3	LinkSpeedA and LinkSpeedB (pins 6 and 7)
		25.4	Link signals
		25.5	Subsytem signals
	25.5.1	Memory configuration
			Subsystem register locations
	25.5.2	Mechanical details
	25.5.3	Installation
	25.5.4	Specification
			Notes
	25.5.5	Ordering Information

26 IMS B408 Frame store TRAM
	26.1	IMS B408 TRAM engineering data
		26.1.1	Introduction
		26.1.2	Pin descriptions
		26.1.3	Pixel Port signals
			Electrical Specification
		26.1.4	Memory Map
		26.1.5	Pixel Port control registers
		26.1.6	Mechanical details
		26.1.7	Installation
		26.1.8	Specification
		26.1.9	Ordering Information

27 IMS B409 Display TRAM
	27.1	IMS B409 TRAM engineering data
		27.1.1	Introduction
		27.1.2	Pin descriptions
		27.1.3	Pixel Bus connectors
		27.1.4	The Pixel channels
			8 bits/pixel mode
			18 bits/pixel mode
			The colour look-up tables
			Video Outputs
		27.1.5	Memory Map
			Pixel Channel Mode select
			The video timing generator
			The Colour look-up tables
		27.1.6	Mechanical details
		27.1.7	Installation
		27.1.8	Specification
		27.1.9	Ordering Information

28 IMS B415 Differential link buffer TRAM
	28.1	Description
	28.2	Pin descriptions
	28.3	Introduction to the IMS B415
	28.4	Principles of Operation
	28.5	Differential Connectors
	28.6	Cables
	28.7	Mechanical details
	28.8	Installation
	28.9	Specification
	28.10	References
	28.11	Ordering Information

29 IMS B418 Flash ROM TRAM
	29.1	Description
		29.1.1	Booting transputer networks with the IMS B418
		29.1.2	Flash ROMs
		29.1.3	The IMS B418 in the development environment
			Bootstrap Mode
			Transparent mode
			Auto-program mode
		29.1.4	Firmware
			Summary of Programming Protocol
		29.1.5	Programming Voltage Generator
		29.1.6	Power-on reset / Power-fail monitor
		29.1.7	Sub-system Pins
		29.1.8	Link select jumpers
		29.1.9	Mode select jumpers
	29.2	Specifications
			Notes
	29.3	Reference
	29.4	Ordering Information

30 IMS B419 Graphics TRAM
	30.1	Description
		30.1.1	Introduction
		30.1.2	Screen sizes
		30.1.3	SubSystem signals
		30.1.4	CVC reset register
		30.1.5	Clock Select Register
		30.1.6	Memory Map
		30.1.7	Pixel clock selection
		30.1.8	Jumper selection
		30.1.9	Video and sync outputs
	30.2	Graphics library software
			Summary of CGI Graphics Library functions
	30.3	Mechanical details
	30.4	Pin descriptions
	30.5	Specification
	30.6	References
	30.7	Ordering Information

31 IMS B420 Vector processing TRAM
	31.1	Introduction
			The IMS T800 Processor
			The ZR34325 Vector/Signal Processor
	31.2	Transputer memory map
	31.3	ZR34325 memory map
	31.4	Mechanical details
	31.5	Specification
	31.6	IMS F000 software library
		31.6.1	Software support
			IMS F000A function calls include:
	31.7	Ordering Information

32 IMS B421 IEEE-488 GPIB TRAM
	32.1	Description
		32.1.1	The IEEE-488 standard
		32.1.2	Companion software package IMS F001
	32.2	Pin descriptions
		32.2.1	Standard TRAM signals
		32.2.2	Subsystem signals
	32.3	Hardware features
		32.3.1	Onboard transputer system
		32.3.2	IEEE-488 Interface
		32.3.3	Electrically Eraseable Read Only Memory (EEROM)
		32.3.4	Power-up/Power-fail detection
		32.3.5	Jumpers
	32.4	Connector pin assignments
		32.4.1	IEEE-488 connector J1
		32.4.2	Auxiliary connector J2
	32.5	Option selection jumpers
		32.5.1	Bus address jumpers, JP1 to JP5
		32.5.2	Device capability jumpers, JP6 and 7
		32.5.3	Bus drive selection jumper, JP8
		32.5.4	Data protect jumper, JP9
	32.6	Hardware information for programmers
		32.6.1	Memory configuration
			Subsystem register locations
		32.6.2	Input port assignments
		32.6.3	Output port assignments
		32.6.4	GPIB control register addresses
		32.6.5	Wait states
		32.6.6	Internal and external reset pulse generation
		32.6.7	EEROM programming
	32.7	Mechanical details
	32.8	Installation
	32.9	Specification
	32.10	Ordering information

33 IMS B422 SCSI TRAM
	33.1	IMS B422 SCSI TRAM engineering data
		33.1.1	Transputer Modules (TRAMs)
		33.1.2	Pin descriptions
			Clockln
			LinkOut0-3
			LinkIn0-3
			LinkSpeedA, LinkSpeedB
			Reset
			Analyse
			notError
		33.1.3	A Brief Description of the Small Computer System Interface
		33.1.4	SCSI Capabilities
		33.1.5	Connecting the IMS B422 to a SCSI bus
		33.1.6	IMS B422 hardware
		33.1.7	Memory map
		33.1.8	IMS F002 board support software
		33.1.9	Structure
		33.1.10	IMS B422 Device Driver
		33.1.11	Initialisation Interface
		33.1.12	Initiator Mode Interface
		33.1.13	Target Mode Interface
		33.1.14	Software Distribution
		33.1.15	Mechanical details
		33.1.16	Installation
		33.1.17	Specification
		33.1.18	References
		33.1.19	Ordering Information

34 IMS B429 Video Image Processing TRAM (VIP)
	34.1	Introduction
	34.2	Architecture
	34.3	Supported operations
		34.3.1	Decimation and interpolation
	34.4	Video input circuit
		34.4.1	Input look-up table (LUT)
	34.5	Memory map
	34.6	Specification
	34.7	Ordering information

35 IMS B430 Prototyping TRAM
	35.1	IMS B430 Prototyping TRAM product overview
			Printed Circuit Board
			Onboard transputer system
			Prototyping area
		35.1.1	Specification
		35.1.2	Ordering Information

36 IMS B431 Ethernet TRAM
	36.1	Specification
	36.2	Ordering Information

Motherboards and other Standard Interface Boards


37 IMS B008 IBM PC Motherboard
	37.1	Description
		37.1.1	Introduction
		37.1.2	TRAM Slots
		37.1.3	System Services
		37.1.4	Link Configuration
		37.1.5	IBM PC Bus Interface
			Link interface
			Host system services
			DMA
			Interrupts
		37.1.6	Link Speeds
	37.2	Specifications
			Mechanical details
			Thermal Information
			Operating and Storage Environments
			Electrical details
	37.3	Connector Pin Assignments
			P1 pin assignments
			P2 pin assignments
	37.4	Jumpers
	37.5	Switches
	37.6	Reference
	37.7	Ordering Information

38 IMS B017 IBM PS/2 Motherboard
	38.1	IMS B017 engineering data
		38.1.1	Description
		38.1.2	TRAM Slots
		38.1.3	System Services
		38.1.4	Micro Channel bus interface
			Link interface
			Host system services
			Interrupts
		38.1.5	Configuration
		38.1.6	Specifications
			Mechanical Details
			Thermal Information
			Operating and Storage Environments
			Electrical Details
		38.1.7	Memory Map
		38.1.8	Connector Pin Assignments
			J3 pin assignments
		38.1.9	References
		38.1.10	Ordering Information

39 IMS B014 VMEbus slave card
	39.1	Description
		39.1.1	VMEbus Interface
		39.1.2	Interrupts
		39.1.3	IMS C004 Control
		39.1.4	System Services Organisation
	39.2	Specification
			Mechanical details
			Thermal details
			Operating and Storage Environments
			Electrical details
			VMEbus capability
	39.3	Ordering Information

40 IMS B016 VMEbus Master/Slave
	40.1	Introduction
			VME Bus
			IMS T801 Transputer
	40.2	Description
		40.2.1	IMS T801 and private SRAM
		40.2.2	Primary Control Registers
		40.2.3	MAP-RAM
		40.2.4	Dual-Access DRAM
		40.2.5	Byte Multiplexor
		40.2.6	VME Features
		40.2.7	F-ROM
		40.2.8	Serial Ports
		40.2.9	PEX Boards
		40.2.10	Real-Time Clock
		40.2.11	Resets and Transputer System Services
		40.2.12	The Front Panel
	40.3	'Hard' Configuration Information
	40.4	Memory Maps
	40.5	Specification
		40.5.1	Mechanical and Thermal Details
		40.5.2	Electrical Details
		40.5.3	VMEbus capability
	40.6	Connector Pin Assignments
	40.7	References
	40.8	Ordering Information

41 IMS B015 NEC 9800 series PC Board
	41.1	Description
		41.1.1	Link connections
		41.1.2	Link speed selection
		41.1.3	System Services
		41.1.4	Up, Down, and Subsystem
		41.1.5	PC interface
		41.1.6	IO Address
		41.1.7	Reset, Analyse and Error registers
		41.1.8	Interface link
			Interrupts
		41.1.9	External power supplies
	41.2	External Connections
	41.3	Specification
	41.4	Ordering Information

42 IMS B012 Double extended eurocard
	42.1	IMS B012 Double Eurocard Motherboard engineering data
		42.1.1	Introduction
		42.1.2	Hardware Description
			Link Connections
			P1 Links
			Switch Configuration Transputer
			Reset Analyse and Error
			Link Termination
			Error Lights
			User Power Connector
			Uncommitted Pins
	42.2	Specifications
			Mechanical Details
			Thermal Information
	42.3	Ordering Information

43 IMS B018 TRAM motherboard
			Ordering Information

44 IMS B300 Ethernet connection system
	44.1	IMS B300 Network connection system engineering data
		44.1.1	Interfaces
		44.1.2	Diagnostic Interfaces
		44.1.3	Protocols
		44.1.4	Performance
		44.1.5	Specification
		44.1.6	Ordering information

Associated Hardware Products



45 IMS B250 VME Rack
	45.1	Front panel
	45.2	Specification
	45.3	Ordering Information

46 IMS CA12 Card Frame Adapter
			Ordering Information

47 Cables for Board Products

Application Notes


48 Dual-In-Line Transputer Modules (TRAMs) (INMOS Technical Note 29)
	48.1	Background
	48.2	Introduction
	48.3	Functional description
		48.3.1	Pinout of size1 module
		48.3.2	Pinout of larger sized modules
		48.3.3	TRAMs with more than one transputer
		48.3.4	Extra pins
		48.3.5	Subsystem signals driven from a TRAM
			Subsystem registers
			Multiple subsystems
		48.3.6	Memory parity
		48.3.7	Memory map
	48.4	Electrical description
		48.4.1	Link outputs
		48.4.2	Link inputs
		48.4.3	notError output
		48.4.4	Reset and analyse inputs
		48.4.5	Clock input
		48.4.6	notError input to subsystem
		48.4.7	GND, VCC
	48.5	Mechanical description
		48.5.1	Width and length
		48.5.2	Vertical dimensions
		48.5.3	Direction of cooling
	48.6	TRAM pins and sockets
		48.6.1	Stackable socket pin
		48.6.2	Through-board sockets
		48.6.3	Subsystem pins and sockets
		48.6.4	Motherboard sockets
	48.7	Mechanical retention of TRAMs
	48.8	Profile drawings

49 Module Motherboard Architecture (INMOS Technical Note 49)
	49.1	Introduction
	49.2	Module motherboard architecture
		49.2.1	Design goals
		49.2.2	Architecture
	49.3	Link configuration
		49.3.1	Pipeline
		49.3.2	IMS C004 link configuration
		49.3.3	T212 pipeline and C004 control
		49.3.4	Software link configuration
	49.4	System control
		49.4.1	Reset, analyse and error
		49.4.2	Up, down and subsystem
		49.4.3	Source of control
		49.4.4	Clock
	49.5	Interface to a separate host
		49.5.1	Link interface
		49.5.2	System control interface
		49.5.3	Interrupts
	49.6	Mechanical considerations
		49.6.1	Dimensions
			Width and length
			Vertical dimensions
		49.6.2	Motherboard sockets
		49.6.3	Mechanical retention of TRAMs
		49.6.4	Module orientation
	49.7	Edge connectors

50 Developing parallel C programs for transputers (INMOS Technical Note 68)
	50.1	Introduction
	50.2	What is the C toolset?
		50.2.1	Introduction
		50.2.2	Software toolset summary
		50.2.3	Software design cycle - single transputer systems
			Edit
			Compile
			Linking
			Boot Strap
			Run
			Debugging
		50.2.4	Software design cycle - multiple transputer systems
			Configure
	50.3	Example problem description
		50.3.1	Introduction
		50.3.2	What is configuration?
	50.4	Using the Dx214 C toolset
		50.4.1	Introduction
		50.4.2	C parallel processing library extensions
		50.4.3	Parallel version on one transputer, all in C
			Setting up a process
			Running the processes in parallel
			Channel communications
			The master process
			The worker process
			Building the upper case example
			Running the single processor version
		50.4.4	Configuring a mufti-processor version using icconf
			Introduction
			Introducing some new tools
			The master process
			The worker process
			Connecting to the external configuration channels
			Writing a configuration script
			Declaring the physical hardware
			Showing physical interconnect
			Interface description
			Wiring things up
			Pulling in the real code
			Placing the processes onto processors
			Building the example
			Running the multi-processor version
	50.5	Conclusions
	50.6	Differences between 3L and icc concurrency library
			Upgrading code to IMS Dx214 from IMS D711
	50.7	Useful hints when writing Dx214 C toolset programs
			Program design methodology
		50.7.1	What if the program will not run?
	50.8	References

Appendices


A Quality and Reliability

B Software Licensing
			End User Licences
			Distribution Licences

C Product Reference Tables
	C.1	Table of Composite Products
	C.2	Table of Board Products and Associated Software

Indexes

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Last modification: 06.12.2010 13:07:14