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T9000 Transputer Hardware Reference Manual

First Edition 1993
INMOS document number: 72-TRN-238-01
356 Pages

© INMOS Limited 1993. INMOS reserves the right to make changes in specifications at any time and without notice. The information furnished by INMOS in this publication is believed to be accurate; however, no responsibility is assumed for its use, nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted under any patents, trademarks or other rights of INMOS.


frontcover 72-TRN-238-01

The T9000 Transputer Hardware Reference Manual provides information on the latest member of the transputer range of microprocessors, the IMS T9000. Transputers are designed to provide extremely high performance in single processor applications and are also designed with hardware and software features for the construction of multiprocessing systems.

Other transputer products include the IMS T225, a 16 bit microprocessor, the 32 bit IMS T4xx series and the IMS T8xx series, which are 32 bit microprocessors with an on-chip 64 bit floating point processor. Details of these and their support devices can be found in The Transputer Databook, which is available as a separate publication. Other transputer related documents, including various application and technical notes, are also available from INMOS.

This manual consists of three parts. Part 1, an overview section, introduces the transputer architecture and then the features and benefits of the IMS T9000 family. Part 2, the IMS T9000 transputer preliminary datasheet, contains more detailed information on the IMS T9000 transputer. Part 3 contains information on the communications support devices and includes the IMS C100 system protocol converter preliminary datasheet, IMS C104 packet routing switch product preview and the IMS C101 parallel DS-link adaptor product preview.

More detailed information on the IMS T9000 family communications devices is in preparation, and will be issued as a separate document, titled the Transputer Networks Manual. It will contain datasheets on the IMS 0104 packet routing switch, the IMS C100 system protocol converter and the IMS C101 parallel DS-Link adaptor.

For full details of the IMS T9000 instructions refer to the T9000 Transputer Instruction Set Manual.

Software and hardware examples given in this databook are outline design studies and are included to illustrate various ways in which transputers can be used. The examples are not intended to provide accurate application designs.

In addition to transputer products the INMOS product range also includes development systems and systems products. For further information regarding INMOS products please contact your local SGS-THOMSON sales outlet.



Notation and nomenclature
	Signal naming conventions
	Timing diagram conventions
	Font conventions
	Transputer product numbers

Part 1: IMS T9000 Product Family Overview

1	Introducing the IMS T9000
	1.1	Performance
	1.2	Multiprocessing
	1.3	Communications support devices
	1.4	Software
	1.5	Applications

2	The IMS T9000 transputer
	2.1	Overview
		2.1.1	Processor
		2.1.2	Hierarchical memory system
		2.1.3	Communications system
		2.1.4	Multiple internal buses
		2.1.5	Control system
		2.1.6	Clocks
	2.2	The transputer architecture
	2.3	Support for concurrent processes
	2.4	Pipelined, superscalar implementation
		2.4.1	The pipeline
	2.5	Hierarchical memory system
		2.5.1	Main cache
			Cache operation
			Use as on-chip RAM
		2.5.2	Workspace cache

3	Simplicity of system design
	3.1	Single 5 MHz clock input
	3.2	Programmable memory interface
	3.3	Control links and configuration
	3.4	Loading and bootstrapping
	3.5	Examples

4	Protection and error handling
	4.1	Error handling
	4.2	Protected mode
		4.2.1	Protected mode processes
		4.2.2	Executing illegal instructions
		4.2.3	Memory management

5	Support for multiprocessing
			Fast interrupt response and process switch
	5.1	The transputer model of concurrency
		5.1.1	Processes and channels
		5.1.2	Program structure
		5.1.3	Multiprocessor programs
	5.2	Other models of concurrency
		5.2.1	Shared memory
	5.3	Hardware scheduler
	5.4	Interrupts, events and timers
	5.5	Shared resources

6	Communication links
	6.1	Using links between transputers
	6.2	Advantages of using links
		6.2.1	Efficiency
		6.2.2	Simplicity
		6.2.3	Hardware independence
	6.3	IMS T9000 links
		6.3.1	Virtual channels
			Virtual links
			Sending packets
			Receiving packets
			The virtual channel processor
		6.3.2	Levels of link protocol
			Packet level protocol
			Token level protocol
			Bit level protocol

7	Network communications
	7.1	Message routing
			Advantages for the programmer
			Separating routers and processors
			Parallel networks
	7.2	The IMS C104
			Wormhole routing
			Minimizing routing delays
			Control links
		7.2.1	Using IMS T9000s with IMS C104s
			Header deletion
			Routing control channels
	7.3	Routing algorithms
		7.3.1	Labeling networks
		7.3.2	Avoiding deadlock

8	Other communications devices
	8.1	Mixing transputer types: the IMS C100
	8.2	Interfacing to peripherals and host systems

9	Software and systems
	9.1	Development software
		9.1.1	Configuration tools
			Hardware description
			Software description
			Mapping software to hardware
			Configuration languages
			Types of networks
		9.1.2	Initializing and loading a network
			Levels of initialization
			Booting a system from link
			Booting a system from ROM
		9.1.3	Host servers
		9.1.4	Debugging
	9.2	IMS T9000 systems products

Part 2: IMS T9000 transputer preliminary data

1	IMS T9000 introduction

2	Pin designations
		Phase locked loops
		Programmable memory interface
		Control system
		Communication links

3	Central processing unit
	3.1	Registers
	3.2	Workspace cache
			Cache operation
	3.3	Processes and concurrency
	3.4	Priority
	3.5	L-processes: local error handling and debugging
	3.6	Timers
	3.7	Block move
	3.8	Semaphores
	3.9	Pipeline
		3.9.1	Grouping of instructions
	3.10	CPU configuration registers
			Initiallptr and InitialWptr

4	Floating point unit
	4.1	Floating point registers
		4.1.1	Floating-point stack
		4.1.2	Floating-point status register
	4.2	Floating point instructions

5	Memory management
	5.1	Protection, stack extension, and logical to physical address translation
		5.1.1	Protection
		5.1.2	Stack extension
		5.1.3	Logical to physical address translation
	5.2	Regions
		5.2.1	Region descriptors
		5.2.2	Non-overlapping regions
	5.3	P-process machine registers
	5.4	Debugging

6	Instruction set
	6.1	Efficiency of encoding
	6.2	Interaction of the processor pipeline and the instruction set
	6.3	Instruction characteristics
	6.4	Instruction set tables
		6.4.1	Primary instructions
		6.4.2	Secondary instructions
			Sequential instructions
			Communication instructions
			Process scheduling instructions
			Initialization and configuration instructions
			Cache operation instructions
			Floating point instructions

7	Performance
	7.1	Integer operations
	7.2	Floating point operations
	7.3	Predefines

8	Control system
	8.1	Overview
		8.1.1	Tiers of handshaking
		8.1.2	Autonomous operation
	8.2	Control system interconnections
	8.3	Control system functional description
		8.3.1	Control links
		8.3.2	Packet handler
		8.3.3	Control unit
			Command handler
			Autonomous control
		8.3.4	System services
	8.4	Control commands
			Error message
		8.4.1	IMS T9000 gross state and validity of commands
	8.5	Errors
		8.5.1	Recording of Errors
		8.5.2	Stand alone mode errors
		8.5.3	Errors on control links
		8.5.4	Post-mortem debugging of IMS T9000 systems
			State delivered to the boot program
	8.6	Configuration
		8.6.1	Booting from link
		8.6.2	Boot from ROM then link
	8.7	Reset levels
		8.7.1	Level 0 - hardware reset
		8.7.2	Level 1 - labelled control network
		8.7.3	Level 2 - configured network
		8.7.4	Level 3 - booted network
		8.7.5	Loading code
		8.7.6	Levels of reset effect

9	Instruction and data cache
	9.1	Cache overview
		9.1.1	Cache organization
	9.2	Cache functional description
		9.2.1	Port crossbar switch and arbiter
		9.2.2	Refill engine
		9.2.3	Replace pointer
	9.3	Cache operation
		9.3.1	Cache request
		9.3.2	Arbitration
			Queueing to ensure fairness
		9.3.3	Cacheable and non-cacheable accesses
			Non-cacheable accesses
			Cacheable accesses
		9.3.4	Cache refill cycles
			Cache refills from 8/16 bit ports
			Write-back cycles
			DMA and cache-refill cycles
	9.4	Cache instructions
		9.4.1	Flushing data from the cache
			Flush dirty cache address (fdca)
			Flush dirty cache line (fdcl)
		9.4.2	Invalidate cache block
			Invalidate cache address (ica)
			Invalidate cache line (icl)
		9.4.3	Cache instruction performance
	9.5	Cache configuration registers
		9.5.1	RamSize and DoRamSize registers
		9.5.2	RamLineNumber, RamAddress and DoAllocate registers
	9.6	Initialization of the cache
		9.6.1	Reset state
		9.6.2	Starting the cache

10	Programmable memory interface
	10.1	Pin functions
		10.1.1	MemData0-63
		10.1.2	MemAddr2-31
		10.1.3	notMemWrB0-3
		10.1.4	notMemRAS0-3
		10.1.5	notMemCAS0-3
		10.1.6	notMemPS0-3
		10.1.7	MemWait
		10.1.8	MemReqIn, MemGranted
		10.1.9	MemReqOut
		10.1.10	notMemBootCE
		10.1.11	notMemRf
		10.1.12	notMemStrobe
	10.2	External bus cycles
		10.2.1	External DRAM cycles
		10.2.2	External non-DRAM cycles
		10.2.3	Bank switching
		10.2.4	Cache refill cycles
			Cache refills from 8/16 bit ports
			Write-back cycles
			Wait states and cache-refill cycles
		10.2.5	External DMA
	10.3	PMI configuration registers
		10.3.1	Bank address registers
			Address registers
			Mask registers
			RAS bits registers
			Format control registers
			DoPMIConfigured register
			Error address register
		10.3.2	Strobe timing registers
			Strobe registers
			Timing control registers
			Refresh control register
			Remap boot bank register
		10.3.3	PMI write lock register
	10.4	PMI errors
		10.4.1	Errors detected by the PMI
			PMI errors signalled by the CPU
			PMI errors signalled by the PMI
	10.5	Initialization of the PMI
		10.5.1	Bootspace allocation
		10.5.2	The boot sequence
		10.5.3	Bootspace timing
	10.6	Booting from ROM
		10.6.1	Booting from EPROM
		10.6.2	Booting from Flash EPROM
		10.6.3	Re-mapping the boot bank
	10.7	PMI AC timing characteristics
			Read cycle
			Write cycle
			Consecutive cycles
			Memory wait

11	Communications
	11.1	Overview
		11.1.1	Channels
			Internal channels
			External channels
		11.1.2	Channel addresses
		11.1.3	Communication instructions
		11.1.4	Efficient variable-length communications
	11.2	Virtual channel processor
		11.2.1	VCP protocol
		11.2.2	Virtual links
		11.2.3	VCP link queues
		11.2.4	Virtual link control blocks
			vl.HeaderCtrl word
			vl.DataQueueLink and vl.AckQueueLink words
	11.3	Operation of the VCP
		11.3.1	Channel states
			Resetting channels
			Stopping channels
	11.4	Resources
	11.5	Byte-stream mode
	11.6	Memory and channel address spaces
		11.6.1	Channel address space
		11.6.2	Memory allocation for virtual links
			Memory start value register
			Minimum invalid virtual channel register
			External resource channel base register
	11.7	VCP configuration registers
		11.7.1	VCP command register
		11.7.2	VCP status register
		11.7.3	Header area base register
		11.7.4	Header offset registers
		11.7.5	Packet header limit registers
		11.7.6	VCP link mode registers
		11.7.7	ChanWriteLock
	11.8	Initialization of the VCP
		11.8.1	VCP state on start up
		11.8.2	VCP state following reset
	11.9	Errors
			Null buffer pointers

12	Events
			Input event channel
			Output event channel
			Use of event channels with interrupts
	12.1	Event channel addresses
	12.2	Event channel state

13	Data/Strobe links
	13.1	Link format and protocol
	13.2	Link functional description
	13.3	Low-level flow control
	13.4	Link speed select
	13.5	Errors on DS-Links
		13.5.1	Reliable links
			Handling of errors on reliable links
		13.5.2	Unreliable links
	13.6	Link configuration registers
	13.7	Initialization
		13.7.1	Link state on start up
		13.7.2	Link state following reset
	13.8	Link connections
	13.9	DS-Link timings

14	Clocking phase locked loops
	14.1	Clock input
	14.2	PLL decoupling
	14.3	Processor speed selection
	14.4	Processor clock output
	14.5	ClockIn timings
	14.6	ProcClockOut timings

15	Configuration register reference guide
	15.1	Configuration bus
	15.2	Subsystem addresses
		15.2.1	Shared registers
	15.3	CPU write locking
	15.4	Subsystem registers
		15.4.1	CPU configuration registers
		15.4.2	PMI configuration registers
			PMI bank address configuration registers
			PMI strobe timing configuration registers
		15.4.3	VCP configuration registers
		15.4.4	System services configuration registers
		15.4.5	Cache configuration registers
		15.4.6	Scheduler configuration registers
		15.4.7	Link configuration registers
		15.4.8	Control link configuration registers

16	Package specifications
	16.1	208 pin CLCC package pinout
	16.2	208 pin CLCC package dimensions
	16.3	208 pin CLCC package thermal characteristics

17	Thermal management
	17.1	Forced air flow cooling
	17.2	Heat sinks
	17.3	Other thermal management techniques

18	Electrical specifications
	18.1	Absolute maximum ratings
	18.2	Operating conditions
	18.3	Power rating

Part 3: Communications support devices

1	IMS C100 system protocol converter preliminary data
	1.1	IMS C100 introduction
	1.2	IMS C100 modes of operation
		1.2.1	Mode pins
		1.2.2	Mode 0: Enables a single T9-series transputer to be used in a T2/T4/T8-series network
		1.2.3	Mode 1: Enables a T2/T4/T8-series system to use a T9-series subsystem
		1.2.4	Mode 2: Enables a T9-series system to use an existing T2/T4/T8-series subsystem
		1.2.5	Mode 3: Enables a T9-series system to use a T2/T4/T8-series subsystem
	1.3	Link protocols
		1.3.1	T2/T4/T8-series oversampled links
		1.3.2	T9-series data/strobe links
			Byte-stream mode
	1.4	Link protocol conversion
		1.4.1	Byte-stream conversion - modes 0 and 2
			Messages from the T9000 to the T2/T4/T8
			Messages from the T2/T4/T8 to the T9000
		1.4.2	Packetized conversion - modes 1 and 3
			Messages from the T2/T4/T8 to the T9000
			Messages from the T9000 to the T2/T4/T8
	1.5	Control protocols
		1.5.1	T2/T4/T8-type control
		1.5.2	T9-type control
			Control link protocols
	1.6	Control protocol conversion
		1.6.1	RAE master control (mode 0)
			Control commands sent by the IMS C100 in RAE master control mode
			Handshake and Error messages received by the IMS C100 from the IMS T9000
			Behavior of the control system in RAE master mode
		1.6.2	CLink0 master control (modes 1, 2 and 3)
			Control commands sent by the controlling processor (IMS T9000) to the IMS C100
			OS-Link 0 special function - modes 2 and 3
			Commands which correspond to the protocol of an unbooted T2/T4/T8 transputer
			Resetting and Analyzing
	1.7	Links
		1.7.1	Data links
			Data link speed pins
			DS-Link speeds in mode 0
			DS-Link speeds in modes 1, 2 and 3
			Errors on DS-Links
			Link connections
		1.7.2	Control links
			Control link speeds
		1.7.3	Starting and resetting links
	1.8	Levels of reset
		1.8.1	Level 0 - hardware reset
		1.8.2	Level 1 - labelled control network
		1.8.3	Level 2 - configured network
		1.8.4	Level 3
		1.8.5	Effects of different levels of reset
	1.9	Configuration
		1.9.1	Configuration space
		1.9.2	Configuration register addresses
		1.9.3	Configuration registers
			System services configuration registers
			Data DS-Link configuration registers
			All data links
			Control link configuration registers
			Write lock registers
	1.10	Electrical specifications
		1.10.1	Absolute maximum ratings
		1.10.2	Operating conditions
	1.11	Recommended decoupling
		1.11.1	Power decoupling
		1.11.2	Phase locked loop decoupling
	1.12	Clocks
		1.12.1	Clock input
	1.13	Timing specifications
		1.13.1	Reset and Analyse timings
			ResetOut and AnalyseOut timings
			TReset and AnalyseIn timings
		1.13.2	ClockIn timings
		1.13.3	DS-Link timings
		1.13.4	OS-Link timings
	1.14	Pin designations
			Control unit
			JTAG support
	1.15	Package specifications
		1.15.1	IMS C100 100 pin cavity-up CQFP package pinout
		1.15.2	100 pin CQFP package dimensions
		1.15.3	IMS C100 100 pin cavity-up PQFP package pinout
		1.15.4	100 pin PQFP package dimensions

2	IMS C104 packet routing switch product preview
	2.1	IMS C104 introduction

3	IMS C101 parallel DS-Link adaptor product preview


A	IMS T9000 special values
	A1	IMS T9000 special values

B	IMS T9000 quick reference guide
	B1	IMS T9000 quick reference guide
		B1.1	Electrical specifications
			B1.1.1	Absolute maximum ratings
			B1.1.2	Operating conditions
			B1.1.3	Power rating
		B1.2	Timing specifications
			B1.2.1	ClockIn timings
			B1.2.2	ProcClockOut timings
			B1.2.3	Programmable memory interface timings
				Read cycle
				Write cycle
				Consecutive cycles
				Memory wait
			B1.2.4	Link timings
		B1.3	Processor speed select
		B1.4	Link speed select
		B1.5	Package details
			B1.5.1	208 pin CLCC package pinout
			B1.5.2	208 pin CLCC package dimensions
			B1.5.3	208 pin CLCC package thermal characteristics


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Last modification: 11/27/2020 8:29:40 PM